1. Field of Invention
Embodiments of the present invention relate generally to semiconductor devices and methods of fabricating the same. More particularly embodiments of the present invention relate to phase change memory devices having dual lower electrodes, and methods of fabricating the same.
2. Description of Related Art
Recently, a phase change memory device has been proposed as a novel semiconductor device. Phase change memory devices have a nonvolatile characteristic, and thus do not lose data stored therein even if power is interrupted. A unit cell of the phase change memory device includes a switching device and a data storage element serially connected to the switching device. The data storage element comprises a lower electrode, a phase change material pattern disposed on the lower electrode, and an upper electrode disposed on the phase change material pattern. The lower electrode generally serves as a heater. When a write current flows through the switching device and the lower electrode, Joule heat is generated at an interface between the phase change material pattern and the lower electrode. The phase change material is changed to a substantially amorphous or crystalline state by the Joule heat.
FIG. 1 is a cross-sectional view of a conventional phase change memory cell.
Referring to FIG. 1, an interconnection 12 is provided on a semiconductor substrate 10. A molding layer 14 is deposited on the substrate having the interconnection 12. A diode layer 16 passing through the molding layer 14 and electrically connected to the interconnection 12 is disposed. The diode layer 16 is composed of first and second semiconductor patterns 16a and 16b, which are sequentially stacked, and serves as a switching device. An interlayer insulating layer 18 is provided on the molding layer 14. The diode layer 16 is electrically connected to a contact plug 20 passing through the interlayer insulating layer 18. The contact plug 20 serves as a lower electrode. A phase change material pattern 22 covering the contact plug 20 is deposited on the interlayer insulating layer 18. A top surface of the phase change material pattern 22 is in contact with an upper electrode 24. The upper electrode 24 is self-aligned with respect to the phase change material pattern 22 and, therefore, has a width equal to a width of the phase change material pattern 22.
To store desired data in the phase change memory cell having the phase change material pattern 22, a write current flowing through the upper electrode 24, the phase change material pattern 22 and the lower electrode 20 has to be applied. According to an amount of the write current, a phase-changed region 26 of the phase change material pattern 22 in contact with the lower electrode 20 is changed to a substantially crystalline or amorphous state. In this case, since the Joule heat is isotropically supplied into the phase change material pattern 22, the phase change material pattern 22 has a hemisphere-shaped phase-changed region 26 therein.
As the phase change material pattern 22, a chalcogenide material layer, for example, a GeSbTe (GST) layer, is widely used. The GST layer readily reacts with conductive materials such as polysilicon. For example, when the GST layer is in direct contact with polysilicon, silicon atoms in the polysilicon layer diffuse into the GST layer, thereby increasing resistance of the GST layer. As a result, characteristics of the GST layer may deteriorate. Therefore, the lower and upper electrodes 20 and 24 in direct contact with the phase change material pattern 22 are formed of a stable conductive layer which does not react with the phase change material pattern 22. Recently, a metal nitride layer such as a titanium nitride layer has been widely used for the lower and upper electrodes 20 and 24.
To reduce the contact resistance between the lower electrode 20 and the diode layer 16, a metal silicide layer 28 is interposed therebetween. In this case, there is a problem that an ohmic contact is not be formed between the titanium nitride layer forming the lower electrode 20, and the metal silicide layer 28 forming the diode electrode, particularly, between the titanium nitride layer and a cobalt silicide layer.
In addition, semiconductor device are generally required to be fabricated with a high integrity and consume a low amount of power. Accordingly, research aimed at decreasing a program operating current or an erase operating current of the phase change memory cell are progressing. One method for reducing an operating current of the phase change memory cell is increasing resistance of a heater. The increased resistance of the heater has a disadvantage of reducing a sensing margin of the phase change memory cell. Therefore, in order to operate a phase change memory cell at a low operating current, there is a need for a lower electrode which can lower contact resistance at an interface between a switching device and the lower electrode, and increase contact resistance at an interface between the lower electrode and a phase change material pattern.